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Design and Performance Analysis of High-Performance Low Power Voltage Mode Sense Amplifier for Static RAM
Divya Dutt, Poornima Mittal, Bhawna Rawat, Brijesh Kumar
DOI: 10.15598/aeee.v20i3.4373
Abstract
In the prominent era of the digital world and Very Large-Scale Integration (VLSI) circuits, Static Random Access Memory (SRAM) provides a vital contribution to low-power and high-speed performance. Sense Amplifiers (SA) are a part of Complementary Metal-Oxide-Semiconductor (CMOS) memories used to read the stored information. This paper indicates a Dual-Voltage, Dual-Tail Level Restoration Voltage Latch Sense Amplifier (DVDTLR-VLSA). The design has been implemented using the LT SPICE tool at 180nm technology node with a 1.8V supply. Performance comparison of existing SA presented in literature with the proposed SA is examined based on different parameters like power, energy, delay, and current. The proposed design maintains power at 2.167uW that is decreased to half as against Dual Switch Transmission Gate Voltage SA (DTGVSA) and shows an appreciable depletion. Also, the current and delay results are improved. Dimensional analysis is also done for the proposed SA to examine the performance. After that, the effect of sleep transistors on the proposed SA examines the performance in comparison to delay and power parameters without sleep transistors. The DVDTLR-VLSA has minimal energy and power. Also, the delay is improved which may be determined more advisable for low-power operations.
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