Helpdesk

Top image

Editorial board

Darius Andriukaitis
Kaunas University of Technology, Lithuania

Radu Arsinte
Technical University of Cluj Napoca, Romania

Ivan Baronak
Slovak University of Technology, Slovakia

Khosrow Behbehani
The University of Texas at Arlington, United States

Mohamed El Hachemi Benbouzid
University of Brest, France

Dalibor Biolek
University of Defence, Czech Republic

Klara Capova
University of Zilina, Slovakia

Ray-Guang Cheng
National Taiwan University of Science and Technology, Taiwan, Province of China

Erik Chromy
UPC Broadband Slovakia, Slovakia

Milan Dado
University of Zilina, Slovakia

Petr Drexler
Brno University of Technology, Czech Republic

Eva Gescheidtova
Brno University of Technology, Czech Republic

Gokhan Hakki Ilk
Ankara University, Turkey

Janusz Jezewski
Institute of Medical Technology and Equipment, Poland

Rene Kalus
VSB - Technical University of Ostrava, Czech Republic

Ivan Kasik
Academy of Sciences of the Czech Republic, Czech Republic

Jan Kohout
University of Defence, Czech Republic

Ondrej Krejcar
University of Hradec Kralove, Czech Republic

Zbigniew Leonowicz
Wroclaw University of Science and Technology, Poland

Miroslaw Luft
Technical University of Radom, Poland

Stanislav Marchevsky
Technical University of Kosice, Slovakia

Jerzy Mikulski
University of Economics in Katowice, Katowice, Poland

Karol Molnar
Honeywell International, Czech Republic

Thang Trung Nguyen
Ton Duc Thang University, Viet Nam

Miloslav Ohlidal
Brno University of Technology, Czech Republic

Neeta Pandey
Delhi Technological University, India

Alex Noel Joseph Raj
Shantou University, China

Marek Penhaker
VSB - Technical University of Ostrava, Czech Republic

Wasiu Oyewole Popoola
The University of Edinburgh, United Kingdom

Roman Prokop
Tomas Bata University in Zlin, Czech Republic

Karol Rastocny
University of Zilina, Slovakia

Marie Richterova
University of Defence, Czech Republic

Gheorghe Sebestyen-Pal
Technical University of Cluj Napoca, Romania

Sergey Vladimirovich Serebriannikov
National Research University "MPEI", Russian Federation

Yuriy Shmaliy
Guanajuato University, Mexico

Vladimir Schejbal
University of Pardubice, Czech Republic

Bohumil Skala
University of West Bohemia in Plzen, Czech Republic

Lorand Szabo
Technical University of Cluj Napoca, Romania

Adam Szelag
Warsaw University of Technology, Poland

Ahmadreza Tabesh
Isfahan University of Technology, Iran, Islamic Republic Of

Mauro Tropea
DIMES Department of University of Calabria, Italy

Viktor Valouch
Academy of Sciences of the Czech Republic, Czech Republic

Jiri Vodrazka
Czech Technical University in Prague, Czech Republic

Miroslav Voznak
VSB - Technical University of Ostrava, Czech Republic

He Wen
Hunan University, China

Otakar Wilfert
Brno University of Technology, Czech Republic


Home Search Mail RSS


Early Area and Power Estimation Model for Rapid System Level Design and Design Space Exploration

Abhishek Narayan Tripathi, Arvind Rajawat

DOI: 10.15598/aeee.v20i1.4229


Abstract

Power and area estimation in the early stage of designing is very critical for a system. This paper presents the neural network-based early area and power estimation model. The flow starts with the training of the neural network model from the selected behavioral level parameters, which imposes to provide accurate estimations. The model accuracy is validated against ITC99 benchmark programs. The run-times are faster than the synthesis run-times. For the ASIC-based designs, the proposed model took 5 seconds, while Synopsys Design Compiler took 5 minutes. In terms of timing, the estimation speed is more than the order of magnitude faster than the conventional synthesis-based approach. The modeling methodology provides a better, accurate, and fast area and power estimations, at an early stage of the Very-Large-Scale Integration (VLSI) design. In addition, the model eliminates the need for synthesis-based exploration and provides the design picking before synthesis.

Keywords


Area estimation; design space exploration; neural network; power estimation; VLSI.

Full Text:

PDF